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<div class="title">xqspipsu_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gad640cfc94f8897693611481fbe12847b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gad640cfc94f8897693611481fbe12847b">XQSPIPSU_HW_H</a></td></tr>
<tr class="memdesc:gad640cfc94f8897693611481fbe12847b"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="group__qspipsu.html#gad640cfc94f8897693611481fbe12847b">More...</a><br/></td></tr>
<tr class="separator:gad640cfc94f8897693611481fbe12847b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac15438de9bb521c5731be71e6bc31ebb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gac15438de9bb521c5731be71e6bc31ebb">XQspiPsu_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:gac15438de9bb521c5731be71e6bc31ebb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the 32 bit register value.  <a href="group__qspipsu.html#gac15438de9bb521c5731be71e6bc31ebb">More...</a><br/></td></tr>
<tr class="separator:gac15438de9bb521c5731be71e6bc31ebb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf9672b4f2ec43ccf15204998ff3df728"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gaf9672b4f2ec43ccf15204998ff3df728">XQspiPsu_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:gaf9672b4f2ec43ccf15204998ff3df728"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the 32 bit register value.  <a href="group__qspipsu.html#gaf9672b4f2ec43ccf15204998ff3df728">More...</a><br/></td></tr>
<tr class="separator:gaf9672b4f2ec43ccf15204998ff3df728"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gab88bcdb0f53b21b79cd0805cfd14cb89">XQspiPsu_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="group__qspipsu.html#gac15438de9bb521c5731be71e6bc31ebb">XQspiPsu_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a register.  <a href="group__qspipsu.html#gab88bcdb0f53b21b79cd0805cfd14cb89">More...</a><br/></td></tr>
<tr class="separator:gab88bcdb0f53b21b79cd0805cfd14cb89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga584ee0482b95d3f49353438ca58fb180"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga584ee0482b95d3f49353438ca58fb180">XQspiPsu_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)&#160;&#160;&#160;<a class="el" href="group__qspipsu.html#gaf9672b4f2ec43ccf15204998ff3df728">XQspiPsu_Out32</a>((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:ga584ee0482b95d3f49353438ca58fb180"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a register.  <a href="group__qspipsu.html#ga584ee0482b95d3f49353438ca58fb180">More...</a><br/></td></tr>
<tr class="separator:ga584ee0482b95d3f49353438ca58fb180"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device Base Address</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Below macros gives QSPI, QSPIPSU base address. </p>
</div></td></tr>
<tr class="memitem:ga49734e127e6359b15c1ce7f117748c36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a>&#160;&#160;&#160;0XFF0F0000U</td></tr>
<tr class="memdesc:ga49734e127e6359b15c1ce7f117748c36"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Base Address.  <a href="group__qspipsu.html#ga49734e127e6359b15c1ce7f117748c36">More...</a><br/></td></tr>
<tr class="separator:ga49734e127e6359b15c1ce7f117748c36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga137198cf9ed99131ff88af7201399ebe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga137198cf9ed99131ff88af7201399ebe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_BASEADDR</b>&#160;&#160;&#160;0xFF0F0100U</td></tr>
<tr class="separator:ga137198cf9ed99131ff88af7201399ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31c5986aae494ee1e370e7aa1cb9fecc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga31c5986aae494ee1e370e7aa1cb9fecc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_OFFSET</b>&#160;&#160;&#160;0x100U</td></tr>
<tr class="separator:ga31c5986aae494ee1e370e7aa1cb9fecc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPS Enable Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>QSPIPSU Enable Register </p>
</div></td></tr>
<tr class="memitem:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gab5bb698f82719c1ffdf5055dd5ebf939">XQSPIPS_EN_REG</a>&#160;&#160;&#160;( ( <a class="el" href="group__qspipsu.html#ga49734e127e6359b15c1ce7f117748c36">XQSPIPS_BASEADDR</a> ) + 0X00000014U )</td></tr>
<tr class="memdesc:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPS_EN_REG.  <a href="group__qspipsu.html#gab5bb698f82719c1ffdf5055dd5ebf939">More...</a><br/></td></tr>
<tr class="separator:gab5bb698f82719c1ffdf5055dd5ebf939"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga125c3a3536e6dca9a5f07f44d2d1e01a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga125c3a3536e6dca9a5f07f44d2d1e01a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPS_EN_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga125c3a3536e6dca9a5f07f44d2d1e01a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2313fb0e43c0f5eb2c95bd9a1260e22d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2313fb0e43c0f5eb2c95bd9a1260e22d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPS_EN_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga2313fb0e43c0f5eb2c95bd9a1260e22d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96889f957fdaacfd54de755e5ee65d63"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga96889f957fdaacfd54de755e5ee65d63"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPS_EN_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
<tr class="separator:ga96889f957fdaacfd54de755e5ee65d63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU configuration Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring GQSPI controller </p>
</div></td></tr>
<tr class="memitem:ga1d76a2f706f3988da79345132e484303"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga1d76a2f706f3988da79345132e484303">XQSPIPSU_CFG_OFFSET</a>&#160;&#160;&#160;0X00000000U</td></tr>
<tr class="memdesc:ga1d76a2f706f3988da79345132e484303"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_CFG.  <a href="group__qspipsu.html#ga1d76a2f706f3988da79345132e484303">More...</a><br/></td></tr>
<tr class="separator:ga1d76a2f706f3988da79345132e484303"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad2fafa33e883a7f13ddeecc632296253"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad2fafa33e883a7f13ddeecc632296253"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_MODE_EN_SHIFT</b>&#160;&#160;&#160;30U</td></tr>
<tr class="separator:gad2fafa33e883a7f13ddeecc632296253"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga49938026c5a387a152326b1d6b873f2f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga49938026c5a387a152326b1d6b873f2f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_MODE_EN_WIDTH</b>&#160;&#160;&#160;2U</td></tr>
<tr class="separator:ga49938026c5a387a152326b1d6b873f2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60acbb4fc55232d1fdcf12f88b7642a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga60acbb4fc55232d1fdcf12f88b7642a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_MODE_EN_MASK</b>&#160;&#160;&#160;0XC0000000U</td></tr>
<tr class="separator:ga60acbb4fc55232d1fdcf12f88b7642a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga014fda4357af943315be062a5076c250"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga014fda4357af943315be062a5076c250"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_MODE_EN_DMA_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
<tr class="separator:ga014fda4357af943315be062a5076c250"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae9d42317afd1df665f226893db2c415a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae9d42317afd1df665f226893db2c415a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT</b>&#160;&#160;&#160;29U</td></tr>
<tr class="separator:gae9d42317afd1df665f226893db2c415a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a23207d51d07830c00518b58c25b5a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6a23207d51d07830c00518b58c25b5a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga6a23207d51d07830c00518b58c25b5a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf73da674276d7ba7aca39bfe08f6b284"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf73da674276d7ba7aca39bfe08f6b284"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK</b>&#160;&#160;&#160;0X20000000U</td></tr>
<tr class="separator:gaf73da674276d7ba7aca39bfe08f6b284"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb3f588d757d3e0c4747df0cfc57317d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacb3f588d757d3e0c4747df0cfc57317d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_START_GEN_FIFO_SHIFT</b>&#160;&#160;&#160;28U</td></tr>
<tr class="separator:gacb3f588d757d3e0c4747df0cfc57317d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac786c85b0506ab185104e641fc951715"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac786c85b0506ab185104e641fc951715"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_START_GEN_FIFO_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gac786c85b0506ab185104e641fc951715"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee84f57a34e2430e16738110aa975deb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaee84f57a34e2430e16738110aa975deb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_START_GEN_FIFO_MASK</b>&#160;&#160;&#160;0X10000000U</td></tr>
<tr class="separator:gaee84f57a34e2430e16738110aa975deb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6ed4a02784f14b06fac16a09b68642c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad6ed4a02784f14b06fac16a09b68642c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_ENDIAN_SHIFT</b>&#160;&#160;&#160;26U</td></tr>
<tr class="separator:gad6ed4a02784f14b06fac16a09b68642c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95de107fc3ee72382e02fd1adbb9fbd3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga95de107fc3ee72382e02fd1adbb9fbd3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_ENDIAN_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga95de107fc3ee72382e02fd1adbb9fbd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeac40499ca4034f931b2ea531a6013fc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeac40499ca4034f931b2ea531a6013fc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_ENDIAN_MASK</b>&#160;&#160;&#160;0X04000000U</td></tr>
<tr class="separator:gaeac40499ca4034f931b2ea531a6013fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81dae524dc35a12cfbb4651bb9560f0e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga81dae524dc35a12cfbb4651bb9560f0e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_EN_POLL_TO_SHIFT</b>&#160;&#160;&#160;20U</td></tr>
<tr class="separator:ga81dae524dc35a12cfbb4651bb9560f0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2ddbd54acd18f02b4672c2186312a0b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf2ddbd54acd18f02b4672c2186312a0b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_EN_POLL_TO_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaf2ddbd54acd18f02b4672c2186312a0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad33bcd2c755cb68771f24f4734be5f33"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad33bcd2c755cb68771f24f4734be5f33"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_EN_POLL_TO_MASK</b>&#160;&#160;&#160;0X00100000U</td></tr>
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<tr class="memitem:ga771373ef1eae2f3c9a82a04d3c0c358a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga771373ef1eae2f3c9a82a04d3c0c358a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_WP_HOLD_SHIFT</b>&#160;&#160;&#160;19U</td></tr>
<tr class="separator:ga771373ef1eae2f3c9a82a04d3c0c358a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95b22cb1e6ee4b22d96555e11a0347db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga95b22cb1e6ee4b22d96555e11a0347db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_WP_HOLD_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga95b22cb1e6ee4b22d96555e11a0347db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84bdb1d6152946bdcd559ea1b602356f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga84bdb1d6152946bdcd559ea1b602356f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_WP_HOLD_MASK</b>&#160;&#160;&#160;0X00080000U</td></tr>
<tr class="separator:ga84bdb1d6152946bdcd559ea1b602356f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad64ffc186724c821d7cc55b4aeb49be1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad64ffc186724c821d7cc55b4aeb49be1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
<tr class="separator:gad64ffc186724c821d7cc55b4aeb49be1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37f707d372fbcfc37c745ff62cd8fb8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga37f707d372fbcfc37c745ff62cd8fb8c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_BAUD_RATE_DIV_MASK</b>&#160;&#160;&#160;0X00000038U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_CLK_PHA_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_CLK_PHA_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_CLK_PHA_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_CLK_POL_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga16ef5f7f509807b0b13ad5726d9f74e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga16ef5f7f509807b0b13ad5726d9f74e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_CLK_POL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga0ba50355ead654fc778b5a499d1b0fcd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0ba50355ead654fc778b5a499d1b0fcd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_CFG_CLK_POL_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU LQSPI Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring LQSPI </p>
</div></td></tr>
<tr class="memitem:ga02a2df38913ec3616e70351637cbbb50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga02a2df38913ec3616e70351637cbbb50">XQSPIPSU_LQSPI_CR_OFFSET</a>&#160;&#160;&#160;0X000000A0U</td></tr>
<tr class="memdesc:ga02a2df38913ec3616e70351637cbbb50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_LQSPI.  <a href="group__qspipsu.html#ga02a2df38913ec3616e70351637cbbb50">More...</a><br/></td></tr>
<tr class="separator:ga02a2df38913ec3616e70351637cbbb50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5bfff58ddca187becec7c533cf355fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gac5bfff58ddca187becec7c533cf355fe">XQSPIPSU_LQSPI_CR_LINEAR_MASK</a>&#160;&#160;&#160;0x80000000U</td></tr>
<tr class="memdesc:gac5bfff58ddca187becec7c533cf355fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">LQSPI mode enable.  <a href="group__qspipsu.html#gac5bfff58ddca187becec7c533cf355fe">More...</a><br/></td></tr>
<tr class="separator:gac5bfff58ddca187becec7c533cf355fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga6fbc52b88d443b2a5ea258ff83ef71f2">XQSPIPSU_LQSPI_CR_TWO_MEM_MASK</a>&#160;&#160;&#160;0x40000000U</td></tr>
<tr class="memdesc:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both memories or one.  <a href="group__qspipsu.html#ga6fbc52b88d443b2a5ea258ff83ef71f2">More...</a><br/></td></tr>
<tr class="separator:ga6fbc52b88d443b2a5ea258ff83ef71f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66a4736f3e48910c8ba8dc2999b16558"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga66a4736f3e48910c8ba8dc2999b16558">XQSPIPSU_LQSPI_CR_SEP_BUS_MASK</a>&#160;&#160;&#160;0x20000000U</td></tr>
<tr class="memdesc:ga66a4736f3e48910c8ba8dc2999b16558"><td class="mdescLeft">&#160;</td><td class="mdescRight">Separate memory bus.  <a href="group__qspipsu.html#ga66a4736f3e48910c8ba8dc2999b16558">More...</a><br/></td></tr>
<tr class="separator:ga66a4736f3e48910c8ba8dc2999b16558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gaa7502d70b7ddd899d5bf8bba3f23d70e">XQSPIPSU_LQSPI_CR_U_PAGE_MASK</a>&#160;&#160;&#160;0x10000000U</td></tr>
<tr class="memdesc:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="group__qspipsu.html#gaa7502d70b7ddd899d5bf8bba3f23d70e">More...</a><br/></td></tr>
<tr class="separator:gaa7502d70b7ddd899d5bf8bba3f23d70e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5406192835c4f1d618b56626790628b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga5406192835c4f1d618b56626790628b1">XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK</a>&#160;&#160;&#160;0x01000000U</td></tr>
<tr class="memdesc:ga5406192835c4f1d618b56626790628b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper memory page.  <a href="group__qspipsu.html#ga5406192835c4f1d618b56626790628b1">More...</a><br/></td></tr>
<tr class="separator:ga5406192835c4f1d618b56626790628b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0eecbc04289c520b605393012c8715ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga0eecbc04289c520b605393012c8715ff">XQSPIPSU_LQSPI_CR_MODE_EN_MASK</a>&#160;&#160;&#160;0x02000000U</td></tr>
<tr class="memdesc:ga0eecbc04289c520b605393012c8715ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable mode bits.  <a href="group__qspipsu.html#ga0eecbc04289c520b605393012c8715ff">More...</a><br/></td></tr>
<tr class="separator:ga0eecbc04289c520b605393012c8715ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40238108ef1f0763edaf8adc59c03d72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga40238108ef1f0763edaf8adc59c03d72">XQSPIPSU_LQSPI_CR_MODE_ON_MASK</a>&#160;&#160;&#160;0x01000000U</td></tr>
<tr class="memdesc:ga40238108ef1f0763edaf8adc59c03d72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode on.  <a href="group__qspipsu.html#ga40238108ef1f0763edaf8adc59c03d72">More...</a><br/></td></tr>
<tr class="separator:ga40238108ef1f0763edaf8adc59c03d72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3cd6ea3b67401b777b26365937e9c97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gad3cd6ea3b67401b777b26365937e9c97">XQSPIPSU_LQSPI_CR_MODE_BITS_MASK</a>&#160;&#160;&#160;0x00FF0000U</td></tr>
<tr class="memdesc:gad3cd6ea3b67401b777b26365937e9c97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode value for dual I/O or quad I/O.  <a href="group__qspipsu.html#gad3cd6ea3b67401b777b26365937e9c97">More...</a><br/></td></tr>
<tr class="separator:gad3cd6ea3b67401b777b26365937e9c97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad327ae631cb6e447615bc9534738af72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gad327ae631cb6e447615bc9534738af72">XQSPIPS_LQSPI_CR_INST_MASK</a>&#160;&#160;&#160;0x000000FFU</td></tr>
<tr class="memdesc:gad327ae631cb6e447615bc9534738af72"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read instr code.  <a href="group__qspipsu.html#gad327ae631cb6e447615bc9534738af72">More...</a><br/></td></tr>
<tr class="separator:gad327ae631cb6e447615bc9534738af72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6f187c067994aa193d43051cb5fef0db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga6f187c067994aa193d43051cb5fef0db">XQSPIPS_LQSPI_CR_RST_STATE</a>&#160;&#160;&#160;0x80000003U</td></tr>
<tr class="memdesc:ga6f187c067994aa193d43051cb5fef0db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default LQSPI CR value.  <a href="group__qspipsu.html#ga6f187c067994aa193d43051cb5fef0db">More...</a><br/></td></tr>
<tr class="separator:ga6f187c067994aa193d43051cb5fef0db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2b4818a62cb0d5671e7dee6130165b09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga2b4818a62cb0d5671e7dee6130165b09">XQSPIPS_LQSPI_CR_4_BYTE_STATE</a>&#160;&#160;&#160;0x88000013U</td></tr>
<tr class="memdesc:ga2b4818a62cb0d5671e7dee6130165b09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default 4 Byte LQSPI CR value.  <a href="group__qspipsu.html#ga2b4818a62cb0d5671e7dee6130165b09">More...</a><br/></td></tr>
<tr class="separator:ga2b4818a62cb0d5671e7dee6130165b09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c05a7421b8aea31df3d026189282cce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga3c05a7421b8aea31df3d026189282cce">XQSPIPS_LQSPI_CFG_RST_STATE</a>&#160;&#160;&#160;0x800238C1U</td></tr>
<tr class="memdesc:ga3c05a7421b8aea31df3d026189282cce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default LQSPI CFG value.  <a href="group__qspipsu.html#ga3c05a7421b8aea31df3d026189282cce">More...</a><br/></td></tr>
<tr class="separator:ga3c05a7421b8aea31df3d026189282cce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Interrupt Status Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>QSPIPSU Interrupt Status Register </p>
</div></td></tr>
<tr class="memitem:gadae24d033fb12577e3e4eda5427a950a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gadae24d033fb12577e3e4eda5427a950a">XQSPIPSU_ISR_OFFSET</a>&#160;&#160;&#160;0X00000004U</td></tr>
<tr class="memdesc:gadae24d033fb12577e3e4eda5427a950a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_ISR.  <a href="group__qspipsu.html#gadae24d033fb12577e3e4eda5427a950a">More...</a><br/></td></tr>
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<tr class="memitem:gacd6a2bb2a65244bdd203cb9d6106f9bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd6a2bb2a65244bdd203cb9d6106f9bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXEMPTY_SHIFT</b>&#160;&#160;&#160;11U</td></tr>
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<tr class="memitem:gabca87ef79796944b674376eb004962aa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabca87ef79796944b674376eb004962aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gafa1357dd40fff82a11471d589edc8c24"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafa1357dd40fff82a11471d589edc8c24"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXEMPTY_MASK</b>&#160;&#160;&#160;0X00000800U</td></tr>
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<tr class="memitem:gaf4d2280070de1ccdfcb84868bbcb71ff"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf4d2280070de1ccdfcb84868bbcb71ff"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFOFULL_SHIFT</b>&#160;&#160;&#160;10U</td></tr>
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<tr class="memitem:ga5c041cc59a45645cddfa6d642e72ff1c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5c041cc59a45645cddfa6d642e72ff1c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFOFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gacfa64727ceb72b9607544e92c4076582"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacfa64727ceb72b9607544e92c4076582"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFOFULL_MASK</b>&#160;&#160;&#160;0X00000400U</td></tr>
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<tr class="memitem:ga858bc0bec834ca6fbd0391344f05baf3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga858bc0bec834ca6fbd0391344f05baf3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT</b>&#160;&#160;&#160;9U</td></tr>
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<tr class="memitem:gaf91ae38e48600a5e5bdbdcd7c87ac916"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf91ae38e48600a5e5bdbdcd7c87ac916"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga391f5e49d75dcfa36e3a87602f8bd041"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga391f5e49d75dcfa36e3a87602f8bd041"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFONOT_FULL_MASK</b>&#160;&#160;&#160;0X00000200U</td></tr>
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<tr class="memitem:gaa4941eb6f67e9800ed4f03418b04c81e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa4941eb6f67e9800ed4f03418b04c81e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXEMPTY_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
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<tr class="memitem:gaa914a82f6076b9a807d5dd4e0565e69f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa914a82f6076b9a807d5dd4e0565e69f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaa914a82f6076b9a807d5dd4e0565e69f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab83d8828517dda57f65d558cc4b11a40"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab83d8828517dda57f65d558cc4b11a40"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXEMPTY_MASK</b>&#160;&#160;&#160;0X00000100U</td></tr>
<tr class="separator:gab83d8828517dda57f65d558cc4b11a40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa27a4168a18193d5afee00109049a4dc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa27a4168a18193d5afee00109049a4dc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
<tr class="separator:gaa27a4168a18193d5afee00109049a4dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae8dfd0d31ed4afd6d6a31c822ffe9d0c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae8dfd0d31ed4afd6d6a31c822ffe9d0c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gae8dfd0d31ed4afd6d6a31c822ffe9d0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7928789ab182d71a0360c50c04cfb64"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae7928789ab182d71a0360c50c04cfb64"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_GENFIFOEMPTY_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
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<tr class="memitem:ga5614fb7c43f2295625a1d8ee93a6e0ce"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5614fb7c43f2295625a1d8ee93a6e0ce"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXFULL_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
<tr class="separator:ga5614fb7c43f2295625a1d8ee93a6e0ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68214e35f32f4ce49ab14967949a07ed"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga68214e35f32f4ce49ab14967949a07ed"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga68214e35f32f4ce49ab14967949a07ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab7c9ec748efb6603c9e08ab6c4a19562"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab7c9ec748efb6603c9e08ab6c4a19562"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXFULL_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
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<tr class="memitem:ga1f4f968a1d2a9c7b9134e34a4828160a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1f4f968a1d2a9c7b9134e34a4828160a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXNEMPTY_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
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<tr class="memitem:ga139c17d2d7819552d7d46dda45b2705e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga139c17d2d7819552d7d46dda45b2705e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXNEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga139c17d2d7819552d7d46dda45b2705e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafbb29916b8d3ac4a6a09d4a414f712c8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafbb29916b8d3ac4a6a09d4a414f712c8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_RXNEMPTY_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
<tr class="separator:gafbb29916b8d3ac4a6a09d4a414f712c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXFULL_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
<tr class="separator:ga2cfc1ec9759ece536ea32c8061995bf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1aca5a1f9aa8633ffd3e021f5e8247f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf1aca5a1f9aa8633ffd3e021f5e8247f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaf1aca5a1f9aa8633ffd3e021f5e8247f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e41fe64461cbcea181cbde6ee2d0600"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1e41fe64461cbcea181cbde6ee2d0600"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXFULL_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXNOT_FULL_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
<tr class="separator:ga94f57e0a7160e9f6564c6ff409645928"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb31ee1a6fc9072ee369761a82f86f3a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacb31ee1a6fc9072ee369761a82f86f3a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXNOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_TXNOT_FULL_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga6aeff30c8cc063b806b28cafcfef970e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6670316b327a116df182dae3c7ef14b5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6670316b327a116df182dae3c7ef14b5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga6670316b327a116df182dae3c7ef14b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga52002b54521a589354a12413d6037f55"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga52002b54521a589354a12413d6037f55"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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<tr class="memitem:ga1f6d8d8245874f422d990d496a48c288"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1f6d8d8245874f422d990d496a48c288"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_ISR_WR_TO_CLR_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Interrupt Enable Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for enabling interrupts </p>
</div></td></tr>
<tr class="memitem:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gab8e3a4621239cb556fc8acdd0a6d10b6">XQSPIPSU_IER_OFFSET</a>&#160;&#160;&#160;0X00000008U</td></tr>
<tr class="memdesc:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IER.  <a href="group__qspipsu.html#gab8e3a4621239cb556fc8acdd0a6d10b6">More...</a><br/></td></tr>
<tr class="separator:gab8e3a4621239cb556fc8acdd0a6d10b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9f244e10a82deaa7faf6b30480aea7e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9f244e10a82deaa7faf6b30480aea7e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXEMPTY_SHIFT</b>&#160;&#160;&#160;11U</td></tr>
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<tr class="memitem:ga7e54d921015916bccc3dc9d808962218"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7e54d921015916bccc3dc9d808962218"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga83d2877403883d73ba27978f8a66af0d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga83d2877403883d73ba27978f8a66af0d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXEMPTY_MASK</b>&#160;&#160;&#160;0X00000800U</td></tr>
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<tr class="memitem:ga5c8c577496c48738f26eca00fbeb2997"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5c8c577496c48738f26eca00fbeb2997"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFOFULL_SHIFT</b>&#160;&#160;&#160;10U</td></tr>
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<tr class="memitem:ga6f92b0d136c51e7566363fe3398dcda7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6f92b0d136c51e7566363fe3398dcda7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFOFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga3917dc8f00c02319d3d388cf7053f12d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3917dc8f00c02319d3d388cf7053f12d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFOFULL_MASK</b>&#160;&#160;&#160;0X00000400U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT</b>&#160;&#160;&#160;9U</td></tr>
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<tr class="memitem:ga86506cfcdd6165f72907eacd01e649c5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga86506cfcdd6165f72907eacd01e649c5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFONOT_FULL_MASK</b>&#160;&#160;&#160;0X00000200U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXEMPTY_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga6c158b9b577de62df32984fa3277239c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6c158b9b577de62df32984fa3277239c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXEMPTY_MASK</b>&#160;&#160;&#160;0X00000100U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFOEMPTY_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
<tr class="separator:ga18a196026bbb30c0be2b7f563f1ef514"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8832469d79138702ee460d8dfdc39cd5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8832469d79138702ee460d8dfdc39cd5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFOEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga8832469d79138702ee460d8dfdc39cd5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ca8a77a99447ebec472fa5616aaf075"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0ca8a77a99447ebec472fa5616aaf075"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_GENFIFOEMPTY_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
<tr class="separator:ga0ca8a77a99447ebec472fa5616aaf075"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ebb4704d617d04ca285b961a5f71314"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6ebb4704d617d04ca285b961a5f71314"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXFULL_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
<tr class="separator:ga6ebb4704d617d04ca285b961a5f71314"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga317fad3c0f08202172d5ac7828ba5761"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga317fad3c0f08202172d5ac7828ba5761"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga317fad3c0f08202172d5ac7828ba5761"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5280c9a17c4e4d407af7bdf9fbb9e65"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa5280c9a17c4e4d407af7bdf9fbb9e65"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXFULL_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
<tr class="separator:gaa5280c9a17c4e4d407af7bdf9fbb9e65"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXNEMPTY_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
<tr class="separator:ga37c907c28cfac57681aac4f3d2cc800e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8cbd7d48ffb1fec6de2e0f1d4021b1eb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8cbd7d48ffb1fec6de2e0f1d4021b1eb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXNEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga8cbd7d48ffb1fec6de2e0f1d4021b1eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab0db03f42761412d147a24f70d622bef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab0db03f42761412d147a24f70d622bef"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_RXNEMPTY_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
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<tr class="memitem:ga61d414723ff949466d8262cb09aa1d6c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga61d414723ff949466d8262cb09aa1d6c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXFULL_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
<tr class="separator:ga61d414723ff949466d8262cb09aa1d6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94ef816765a6bc8ed702a9509181e88c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga94ef816765a6bc8ed702a9509181e88c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga94ef816765a6bc8ed702a9509181e88c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4cdf7f8891dbc5262b863311e861d0f5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4cdf7f8891dbc5262b863311e861d0f5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXFULL_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
<tr class="separator:ga4cdf7f8891dbc5262b863311e861d0f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ed916045c6867cc83765192cb2e0de4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ed916045c6867cc83765192cb2e0de4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXNOT_FULL_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
<tr class="separator:ga1ed916045c6867cc83765192cb2e0de4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95c3565a4276ddc0d8e12215eec7b4aa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga95c3565a4276ddc0d8e12215eec7b4aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXNOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga95c3565a4276ddc0d8e12215eec7b4aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15b5075d4c943c71682b5aec6265e3ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga15b5075d4c943c71682b5aec6265e3ec"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_TXNOT_FULL_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
<tr class="separator:ga15b5075d4c943c71682b5aec6265e3ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga344cae10f68de138962c4fae7746880d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga344cae10f68de138962c4fae7746880d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga344cae10f68de138962c4fae7746880d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga41dd4af0f034e73ab8508450efb110df"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga41dd4af0f034e73ab8508450efb110df"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga41dd4af0f034e73ab8508450efb110df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e56e82bc0cf983a788abf916a648244"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7e56e82bc0cf983a788abf916a648244"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
<tr class="separator:ga7e56e82bc0cf983a788abf916a648244"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Interrupt Disable Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for disabling interrupts </p>
</div></td></tr>
<tr class="memitem:ga5eb684785dfb0a249b18126089624b91"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga5eb684785dfb0a249b18126089624b91">XQSPIPSU_IDR_OFFSET</a>&#160;&#160;&#160;0X0000000CU</td></tr>
<tr class="memdesc:ga5eb684785dfb0a249b18126089624b91"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IDR.  <a href="group__qspipsu.html#ga5eb684785dfb0a249b18126089624b91">More...</a><br/></td></tr>
<tr class="separator:ga5eb684785dfb0a249b18126089624b91"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga02b4569f0b80bf6f60ff2a71a2dc39b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga02b4569f0b80bf6f60ff2a71a2dc39b9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXEMPTY_SHIFT</b>&#160;&#160;&#160;11U</td></tr>
<tr class="separator:ga02b4569f0b80bf6f60ff2a71a2dc39b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaebc9edf79074885ff77e4f985095fd50"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaebc9edf79074885ff77e4f985095fd50"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaebc9edf79074885ff77e4f985095fd50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadec77ed3456965cb1d5eff277ee3d033"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadec77ed3456965cb1d5eff277ee3d033"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXEMPTY_MASK</b>&#160;&#160;&#160;0X00000800U</td></tr>
<tr class="separator:gadec77ed3456965cb1d5eff277ee3d033"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga713fffdd4fc3974eacf87cf57bef4d3f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga713fffdd4fc3974eacf87cf57bef4d3f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFOFULL_SHIFT</b>&#160;&#160;&#160;10U</td></tr>
<tr class="separator:ga713fffdd4fc3974eacf87cf57bef4d3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ff53f8472bc264a8e11fc23d98e8dcd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8ff53f8472bc264a8e11fc23d98e8dcd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFOFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga8ff53f8472bc264a8e11fc23d98e8dcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3aa9bfb67d633f855cf6309467b52fc5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3aa9bfb67d633f855cf6309467b52fc5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFOFULL_MASK</b>&#160;&#160;&#160;0X00000400U</td></tr>
<tr class="separator:ga3aa9bfb67d633f855cf6309467b52fc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga049c752447cb8923454ec7cb11a77bac"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga049c752447cb8923454ec7cb11a77bac"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT</b>&#160;&#160;&#160;9U</td></tr>
<tr class="separator:ga049c752447cb8923454ec7cb11a77bac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga627a709f65e7776f529d69ffc2013d7b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga627a709f65e7776f529d69ffc2013d7b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga627a709f65e7776f529d69ffc2013d7b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30efac42afa9c679fcb58d8a2b3fb5c5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga30efac42afa9c679fcb58d8a2b3fb5c5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFONOT_FULL_MASK</b>&#160;&#160;&#160;0X00000200U</td></tr>
<tr class="separator:ga30efac42afa9c679fcb58d8a2b3fb5c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa852f2d66139b8f643e0d7229d0fc678"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa852f2d66139b8f643e0d7229d0fc678"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXEMPTY_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:gaa852f2d66139b8f643e0d7229d0fc678"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa12869c10c832ce654fc31128ef422c2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa12869c10c832ce654fc31128ef422c2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaa12869c10c832ce654fc31128ef422c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc6a96e745d9dadc68a8703a0ca46136"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabc6a96e745d9dadc68a8703a0ca46136"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXEMPTY_MASK</b>&#160;&#160;&#160;0X00000100U</td></tr>
<tr class="separator:gabc6a96e745d9dadc68a8703a0ca46136"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8cd142762c6f566ea03bfb9dd9e26ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab8cd142762c6f566ea03bfb9dd9e26ee"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
<tr class="separator:gab8cd142762c6f566ea03bfb9dd9e26ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69f98bbda5d969b0e344d1b214b12e94"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga69f98bbda5d969b0e344d1b214b12e94"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga69f98bbda5d969b0e344d1b214b12e94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ff79fdfb738b1aa9da7da1b69efaf53"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7ff79fdfb738b1aa9da7da1b69efaf53"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_GENFIFOEMPTY_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
<tr class="separator:ga7ff79fdfb738b1aa9da7da1b69efaf53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga198b57421e658f174db74fe7de2aee54"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga198b57421e658f174db74fe7de2aee54"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXFULL_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
<tr class="separator:ga198b57421e658f174db74fe7de2aee54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaafbbe1eabc3697e78f35cfef8c95dd24"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaafbbe1eabc3697e78f35cfef8c95dd24"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaafbbe1eabc3697e78f35cfef8c95dd24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee75941a2e175942356db9716a116df7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaee75941a2e175942356db9716a116df7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXFULL_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
<tr class="separator:gaee75941a2e175942356db9716a116df7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac558673fbec3d68729349ce4330cbecb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac558673fbec3d68729349ce4330cbecb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXNEMPTY_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
<tr class="separator:gac558673fbec3d68729349ce4330cbecb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5a663c93d8e3be7ac427fc24643a5f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad5a663c93d8e3be7ac427fc24643a5f0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXNEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gad5a663c93d8e3be7ac427fc24643a5f0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac2702dd262b8a4d08c70a4b1f9eaac7e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac2702dd262b8a4d08c70a4b1f9eaac7e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_RXNEMPTY_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
<tr class="separator:gac2702dd262b8a4d08c70a4b1f9eaac7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf096ed6387f093582d64c738bf432c9f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf096ed6387f093582d64c738bf432c9f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXFULL_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
<tr class="separator:gaf096ed6387f093582d64c738bf432c9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6485347e92b591d67a46a58801cfb76d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6485347e92b591d67a46a58801cfb76d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga6485347e92b591d67a46a58801cfb76d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5ccffba2efc6db9680052c18cfa6762"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab5ccffba2efc6db9680052c18cfa6762"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXFULL_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
<tr class="separator:gab5ccffba2efc6db9680052c18cfa6762"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac199858ca94fddec314c837c6e012dc2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac199858ca94fddec314c837c6e012dc2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXNOT_FULL_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
<tr class="separator:gac199858ca94fddec314c837c6e012dc2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4a1915b0626096a00265c1d6574ffac"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac4a1915b0626096a00265c1d6574ffac"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXNOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gac4a1915b0626096a00265c1d6574ffac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8264f6b3a67886b80e596935393e2ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad8264f6b3a67886b80e596935393e2ad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_TXNOT_FULL_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
<tr class="separator:gad8264f6b3a67886b80e596935393e2ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8cd4e034aa2fef80f18f13ed427054a7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8cd4e034aa2fef80f18f13ed427054a7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga8cd4e034aa2fef80f18f13ed427054a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92255aa3166be0f92ad40cdfb118b641"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga92255aa3166be0f92ad40cdfb118b641"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga92255aa3166be0f92ad40cdfb118b641"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e9d89f1bda9e54e94ff046d3ecc7bae"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8e9d89f1bda9e54e94ff046d3ecc7bae"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
<tr class="separator:ga8e9d89f1bda9e54e94ff046d3ecc7bae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac5ad3237e06b306dd09f876dc8a2445f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac5ad3237e06b306dd09f876dc8a2445f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IDR_ALL_MASK</b>&#160;&#160;&#160;0X0FBEU</td></tr>
<tr class="separator:gac5ad3237e06b306dd09f876dc8a2445f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Interrupt Mask Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for masking interrupts </p>
</div></td></tr>
<tr class="memitem:ga1711ff533a11dd37b3d72056050025e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga1711ff533a11dd37b3d72056050025e5">XQSPIPSU_IMR_OFFSET</a>&#160;&#160;&#160;0X00000010U</td></tr>
<tr class="memdesc:ga1711ff533a11dd37b3d72056050025e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_IMR.  <a href="group__qspipsu.html#ga1711ff533a11dd37b3d72056050025e5">More...</a><br/></td></tr>
<tr class="separator:ga1711ff533a11dd37b3d72056050025e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5981d36a9fe0e865d504f31a8d639c0f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5981d36a9fe0e865d504f31a8d639c0f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXEMPTY_SHIFT</b>&#160;&#160;&#160;11U</td></tr>
<tr class="separator:ga5981d36a9fe0e865d504f31a8d639c0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac9d661b97c366df6fbbe75a86c510bfb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac9d661b97c366df6fbbe75a86c510bfb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gac9d661b97c366df6fbbe75a86c510bfb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa05f1119dc47f4e498017a0ec00cf7f6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa05f1119dc47f4e498017a0ec00cf7f6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXEMPTY_MASK</b>&#160;&#160;&#160;0X00000800U</td></tr>
<tr class="separator:gaa05f1119dc47f4e498017a0ec00cf7f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb9c7061650a9e261fe30871e9957281"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeb9c7061650a9e261fe30871e9957281"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFOFULL_SHIFT</b>&#160;&#160;&#160;10U</td></tr>
<tr class="separator:gaeb9c7061650a9e261fe30871e9957281"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf9c01b9a4478556933082bc03189e3e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadf9c01b9a4478556933082bc03189e3e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFOFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gadf9c01b9a4478556933082bc03189e3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d82132b380817721395622000d6174d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d82132b380817721395622000d6174d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFOFULL_MASK</b>&#160;&#160;&#160;0X00000400U</td></tr>
<tr class="separator:ga1d82132b380817721395622000d6174d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga890cda7177e5295b10615e1464e74bdf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga890cda7177e5295b10615e1464e74bdf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT</b>&#160;&#160;&#160;9U</td></tr>
<tr class="separator:ga890cda7177e5295b10615e1464e74bdf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0cde2c77110d998919e66d3cb2c9f65d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0cde2c77110d998919e66d3cb2c9f65d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga0cde2c77110d998919e66d3cb2c9f65d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFONOT_FULL_MASK</b>&#160;&#160;&#160;0X00000200U</td></tr>
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<tr class="memitem:ga4c58fb9c4d2200e242ff450126ec16e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4c58fb9c4d2200e242ff450126ec16e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXEMPTY_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
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<tr class="memitem:gab084b88249b77c770060053bd181a792"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab084b88249b77c770060053bd181a792"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gab084b88249b77c770060053bd181a792"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabfb51b6802fff87a97635bff17bfda93"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabfb51b6802fff87a97635bff17bfda93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXEMPTY_MASK</b>&#160;&#160;&#160;0X00000100U</td></tr>
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<tr class="memitem:ga6c763dd851fea56cc4ad4621c80ab00c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6c763dd851fea56cc4ad4621c80ab00c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
<tr class="separator:ga6c763dd851fea56cc4ad4621c80ab00c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4355b784b5fa03e0e1e6bb71082ca9bb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4355b784b5fa03e0e1e6bb71082ca9bb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga4355b784b5fa03e0e1e6bb71082ca9bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga168b7548d332ccdbbdc64cda2e5b7264"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga168b7548d332ccdbbdc64cda2e5b7264"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_GENFIFOEMPTY_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
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<tr class="memitem:gaec1a53dee68e0b14842ec9f41079d45a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaec1a53dee68e0b14842ec9f41079d45a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXFULL_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
<tr class="separator:gaec1a53dee68e0b14842ec9f41079d45a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a363be77ba1868e042eab54175f4e8f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7a363be77ba1868e042eab54175f4e8f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga7a363be77ba1868e042eab54175f4e8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc2b998de7a0553d2a7fbf46ed7a77a4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadc2b998de7a0553d2a7fbf46ed7a77a4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXFULL_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
<tr class="separator:gadc2b998de7a0553d2a7fbf46ed7a77a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga252089511474b376379e21d03324b338"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga252089511474b376379e21d03324b338"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXNEMPTY_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
<tr class="separator:ga252089511474b376379e21d03324b338"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d8de28ed67afd33cefe17c5218a331a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d8de28ed67afd33cefe17c5218a331a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXNEMPTY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga1d8de28ed67afd33cefe17c5218a331a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7dbd0d93d57a53e985eac025e204891"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae7dbd0d93d57a53e985eac025e204891"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_RXNEMPTY_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
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<tr class="memitem:ga59e00c301549fa522b7eb40dd9e25171"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga59e00c301549fa522b7eb40dd9e25171"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXFULL_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
<tr class="separator:ga59e00c301549fa522b7eb40dd9e25171"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae36a91f727b1d1f5b675407c3e00b1b1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae36a91f727b1d1f5b675407c3e00b1b1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXFULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gae36a91f727b1d1f5b675407c3e00b1b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga62c0013d297f0e5d341514fa3dbdfc4a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga62c0013d297f0e5d341514fa3dbdfc4a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXFULL_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
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<tr class="memitem:gaff16e4c8ff170a151a1bd453730f6ac5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaff16e4c8ff170a151a1bd453730f6ac5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXNOT_FULL_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
<tr class="separator:gaff16e4c8ff170a151a1bd453730f6ac5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf29b6f35625908251f087f7b797c5a0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaaf29b6f35625908251f087f7b797c5a0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXNOT_FULL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaaf29b6f35625908251f087f7b797c5a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6249d92bfccaccc3680ad8287d34ad05"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6249d92bfccaccc3680ad8287d34ad05"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_TXNOT_FULL_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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<tr class="memitem:ga01e8bf0051bc67f9806ea33866163a9c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga01e8bf0051bc67f9806ea33866163a9c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga01e8bf0051bc67f9806ea33866163a9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81be6689170270886c5deea126e8faff"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga81be6689170270886c5deea126e8faff"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga81be6689170270886c5deea126e8faff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6b1f2d368f0fd7b06adf8781d1a9837e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6b1f2d368f0fd7b06adf8781d1a9837e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
<tr class="separator:ga6b1f2d368f0fd7b06adf8781d1a9837e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Enable Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for enabling QSPI controller </p>
</div></td></tr>
<tr class="memitem:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">XQSPIPSU_EN_OFFSET</a>&#160;&#160;&#160;0X00000014U</td></tr>
<tr class="memdesc:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_EN_REG.  <a href="group__qspipsu.html#ga5b7b95790bfeb5bfb3dfd63e4a5e76cc">More...</a><br/></td></tr>
<tr class="separator:ga5b7b95790bfeb5bfb3dfd63e4a5e76cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaf14751d681194856cd71ce71f72e170"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaaf14751d681194856cd71ce71f72e170"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_EN_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:gaaf14751d681194856cd71ce71f72e170"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf1993fd33601de8e57bb2c9c33dd0ef6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf1993fd33601de8e57bb2c9c33dd0ef6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_EN_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gaf1993fd33601de8e57bb2c9c33dd0ef6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga977552f11dd3e4420b3b561de0750157"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga977552f11dd3e4420b3b561de0750157"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_EN_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
<tr class="separator:ga977552f11dd3e4420b3b561de0750157"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU TX Data Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for configuring TXFIFO </p>
</div></td></tr>
<tr class="memitem:ga4884f0160746c6696598ef6dda1fc9ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga4884f0160746c6696598ef6dda1fc9ff">XQSPIPSU_TXD_OFFSET</a>&#160;&#160;&#160;0X0000001CU</td></tr>
<tr class="memdesc:ga4884f0160746c6696598ef6dda1fc9ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_TXD.  <a href="group__qspipsu.html#ga4884f0160746c6696598ef6dda1fc9ff">More...</a><br/></td></tr>
<tr class="separator:ga4884f0160746c6696598ef6dda1fc9ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ff98d251534141c0caa6e4ce9f490a6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7ff98d251534141c0caa6e4ce9f490a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TXD_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga7ff98d251534141c0caa6e4ce9f490a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8524a39fa5536400dd8f54a15d91f0b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8524a39fa5536400dd8f54a15d91f0b8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TXD_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
<tr class="separator:ga8524a39fa5536400dd8f54a15d91f0b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3cc923bfcdf939e66395b7b01a54093"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf3cc923bfcdf939e66395b7b01a54093"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TXD_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
<tr class="separator:gaf3cc923bfcdf939e66395b7b01a54093"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacaedfa6d1462da9c4542f6ece2bf3536"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacaedfa6d1462da9c4542f6ece2bf3536"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TXD_DEPTH</b>&#160;&#160;&#160;64</td></tr>
<tr class="separator:gacaedfa6d1462da9c4542f6ece2bf3536"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU RX Data Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for configuring RXFIFO </p>
</div></td></tr>
<tr class="memitem:ga68b0b4316693414546980dea7baaf0a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga68b0b4316693414546980dea7baaf0a4">XQSPIPSU_RXD_OFFSET</a>&#160;&#160;&#160;0X00000020U</td></tr>
<tr class="memdesc:ga68b0b4316693414546980dea7baaf0a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RXD.  <a href="group__qspipsu.html#ga68b0b4316693414546980dea7baaf0a4">More...</a><br/></td></tr>
<tr class="separator:ga68b0b4316693414546980dea7baaf0a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3812e16ad9153e4c2346531ad88ff01d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3812e16ad9153e4c2346531ad88ff01d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RXD_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga3812e16ad9153e4c2346531ad88ff01d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85e6c7585d7b8d4ddb96cafc3cba1eea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga85e6c7585d7b8d4ddb96cafc3cba1eea"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RXD_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
<tr class="separator:ga85e6c7585d7b8d4ddb96cafc3cba1eea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17d0aaf5e8072f155042fc5189c6808c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga17d0aaf5e8072f155042fc5189c6808c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RXD_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
<tr class="separator:ga17d0aaf5e8072f155042fc5189c6808c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU TX/RX Threshold Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits for configuring TX/RX Threshold </p>
</div></td></tr>
<tr class="memitem:ga33bc760357127168b3a665f969036421"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga33bc760357127168b3a665f969036421">XQSPIPSU_TX_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X00000028U</td></tr>
<tr class="memdesc:ga33bc760357127168b3a665f969036421"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_TX_THRESHOLD.  <a href="group__qspipsu.html#ga33bc760357127168b3a665f969036421">More...</a><br/></td></tr>
<tr class="separator:ga33bc760357127168b3a665f969036421"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga190f5bd11574e5fd648a40d31ba308db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga190f5bd11574e5fd648a40d31ba308db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga190f5bd11574e5fd648a40d31ba308db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31718b5d33dfb588ae195a6ece1ae996"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga31718b5d33dfb588ae195a6ece1ae996"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH</b>&#160;&#160;&#160;6U</td></tr>
<tr class="separator:ga31718b5d33dfb588ae195a6ece1ae996"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb2831272c645a1b392e4f62eaea1448"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeb2831272c645a1b392e4f62eaea1448"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TX_FIFO_THRESHOLD_MASK</b>&#160;&#160;&#160;0X0000003FU</td></tr>
<tr class="separator:gaeb2831272c645a1b392e4f62eaea1448"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9cc4bdd124b82ebee27c06e2af91e884"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9cc4bdd124b82ebee27c06e2af91e884"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL</b>&#160;&#160;&#160;0X01U</td></tr>
<tr class="separator:ga9cc4bdd124b82ebee27c06e2af91e884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga97be55c27b71a154877fb5f919d627f1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga97be55c27b71a154877fb5f919d627f1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_THRESHOLD_OFFSET</b>&#160;&#160;&#160;0X0000002CU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH</b>&#160;&#160;&#160;6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_FIFO_THRESHOLD_MASK</b>&#160;&#160;&#160;0X0000003FU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL</b>&#160;&#160;&#160;0X01U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RXFIFO_THRESHOLD_OPT</b>&#160;&#160;&#160;32U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU GPIO Register information</div></td></tr>
<tr class="memitem:gad50a54ee932051b2fed093ef6f2e8a12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gad50a54ee932051b2fed093ef6f2e8a12">XQSPIPSU_GPIO_OFFSET</a>&#160;&#160;&#160;0X00000030U</td></tr>
<tr class="memdesc:gad50a54ee932051b2fed093ef6f2e8a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GPIO.  <a href="group__qspipsu.html#gad50a54ee932051b2fed093ef6f2e8a12">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GPIO_WP_N_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GPIO_WP_N_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gafc706224e94b8b9aae93d1bb14d244bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafc706224e94b8b9aae93d1bb14d244bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GPIO_WP_N_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Loopback Master Clock Delay Adjustment Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring loopback </p>
</div></td></tr>
<tr class="memitem:ga4636d144794bb35424cacd6f6d49781a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga4636d144794bb35424cacd6f6d49781a">XQSPIPSU_LPBK_DLY_ADJ_OFFSET</a>&#160;&#160;&#160;0X00000038U</td></tr>
<tr class="memdesc:ga4636d144794bb35424cacd6f6d49781a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_LPBK_DLY_ADJ.  <a href="group__qspipsu.html#ga4636d144794bb35424cacd6f6d49781a">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
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<tr class="memitem:ga6f55f2f44799611f946baf8b8e71d76f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6f55f2f44799611f946baf8b8e71d76f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK</b>&#160;&#160;&#160;0X00000018U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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<tr class="memitem:ga5b5b0de93e54b1d188ea9b6bc16b416e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5b5b0de93e54b1d188ea9b6bc16b416e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK</b>&#160;&#160;&#160;0X00000007U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU GEN_FIFO Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring GENFIFO </p>
</div></td></tr>
<tr class="memitem:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga3bfe2023b6a6ce56e9d13f130bd1c86d">XQSPIPSU_GEN_FIFO_OFFSET</a>&#160;&#160;&#160;0X00000040U</td></tr>
<tr class="memdesc:ga3bfe2023b6a6ce56e9d13f130bd1c86d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GEN_FIFO.  <a href="group__qspipsu.html#ga3bfe2023b6a6ce56e9d13f130bd1c86d">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_DATA_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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<tr class="memitem:gafea2a1db0d2754b88eee5bda086319cc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafea2a1db0d2754b88eee5bda086319cc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_DATA_WIDTH</b>&#160;&#160;&#160;20U</td></tr>
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<tr class="memitem:ga07331f7d9961866bde081f89fe2c45c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07331f7d9961866bde081f89fe2c45c7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_DATA_MASK</b>&#160;&#160;&#160;0X000FFFFFU</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Select Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for selection GQSPI/LQSPI controller </p>
</div></td></tr>
<tr class="memitem:ga84156abbc51d17b988b1e82c584be10d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga84156abbc51d17b988b1e82c584be10d">XQSPIPSU_SEL_OFFSET</a>&#160;&#160;&#160;0X00000044U</td></tr>
<tr class="memdesc:ga84156abbc51d17b988b1e82c584be10d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_SEL.  <a href="group__qspipsu.html#ga84156abbc51d17b988b1e82c584be10d">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_SEL_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_SEL_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga059a8d7515b5a652d5c11c01257cefde"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga059a8d7515b5a652d5c11c01257cefde"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_SEL_LQSPI_MASK</b>&#160;&#160;&#160;0X0U</td></tr>
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<tr class="memitem:ga96c52e688b4bfc308adeb894c7548469"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga96c52e688b4bfc308adeb894c7548469"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_SEL_GQSPI_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU FIFO Control Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for controlling TXFIFO and RXFIFO </p>
</div></td></tr>
<tr class="memitem:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gac14f429fa7d15b5c4bf2808ed08e7120">XQSPIPSU_FIFO_CTRL_OFFSET</a>&#160;&#160;&#160;0X0000004CU</td></tr>
<tr class="memdesc:gac14f429fa7d15b5c4bf2808ed08e7120"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_FIFO_CTRL.  <a href="group__qspipsu.html#gac14f429fa7d15b5c4bf2808ed08e7120">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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<tr class="memitem:gaf91054c38b75882abb7ae5d175eeca5d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf91054c38b75882abb7ae5d175eeca5d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gacf6c7a98e1c31d8c041efac8b94eeb52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacf6c7a98e1c31d8c041efac8b94eeb52"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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<tr class="memitem:ga4438ebabb66d07f63394c60474cb9a5b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4438ebabb66d07f63394c60474cb9a5b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga4438ebabb66d07f63394c60474cb9a5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f0ff603545f3c59f2ae76c2e00be87c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1f0ff603545f3c59f2ae76c2e00be87c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga1f0ff603545f3c59f2ae76c2e00be87c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad8ec48f6a6bdafe46c76289e9c11f877"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad8ec48f6a6bdafe46c76289e9c11f877"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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<tr class="memitem:ga8aa72ade570a1a72ac2fab8dde1e1b8d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8aa72ade570a1a72ac2fab8dde1e1b8d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga8aa72ade570a1a72ac2fab8dde1e1b8d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1c84b7591852289757c0c12f19f6824"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac1c84b7591852289757c0c12f19f6824"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gac1c84b7591852289757c0c12f19f6824"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga636d32a41e6eb12228ab4544c8a89dd8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga636d32a41e6eb12228ab4544c8a89dd8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
<tr class="separator:ga636d32a41e6eb12228ab4544c8a89dd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU GENFIFO Threshold Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring GENFIFO threshold </p>
</div></td></tr>
<tr class="memitem:ga5a8034417fd3c9846c968679c1cad859"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga5a8034417fd3c9846c968679c1cad859">XQSPIPSU_GF_THRESHOLD_OFFSET</a>&#160;&#160;&#160;0X00000050U</td></tr>
<tr class="memdesc:ga5a8034417fd3c9846c968679c1cad859"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GF_THRESHOLD.  <a href="group__qspipsu.html#ga5a8034417fd3c9846c968679c1cad859">More...</a><br/></td></tr>
<tr class="separator:ga5a8034417fd3c9846c968679c1cad859"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d5959168d250e4f7494732ed29d65ce"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6d5959168d250e4f7494732ed29d65ce"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga6d5959168d250e4f7494732ed29d65ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6cda67575b7282414c10d9ca86a014e6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6cda67575b7282414c10d9ca86a014e6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH</b>&#160;&#160;&#160;5U</td></tr>
<tr class="separator:ga6cda67575b7282414c10d9ca86a014e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64f95a614341a1767e27cf852998c3c4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga64f95a614341a1767e27cf852998c3c4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_THRESHOLD_MASK</b>&#160;&#160;&#160;0X0000001FU</td></tr>
<tr class="separator:ga64f95a614341a1767e27cf852998c3c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1a0209b2e67ec12bdbca254b3eb4bf7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1a0209b2e67ec12bdbca254b3eb4bf7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL</b>&#160;&#160;&#160;0X10U</td></tr>
<tr class="separator:gab1a0209b2e67ec12bdbca254b3eb4bf7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Poll configuration Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring Poll feature </p>
</div></td></tr>
<tr class="memitem:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gaf657fc3a38e22e512c0f7cf03bda1ad7">XQSPIPSU_POLL_CFG_OFFSET</a>&#160;&#160;&#160;0X00000054U</td></tr>
<tr class="memdesc:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_POLL_CFG.  <a href="group__qspipsu.html#gaf657fc3a38e22e512c0f7cf03bda1ad7">More...</a><br/></td></tr>
<tr class="separator:gaf657fc3a38e22e512c0f7cf03bda1ad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga05f3a78b23efc4e8cdc730bff2f35330"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga05f3a78b23efc4e8cdc730bff2f35330"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT</b>&#160;&#160;&#160;31U</td></tr>
<tr class="separator:ga05f3a78b23efc4e8cdc730bff2f35330"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13569fde078dbbfaac679afaaef4c2b1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga13569fde078dbbfaac679afaaef4c2b1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga13569fde078dbbfaac679afaaef4c2b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga651ea64178b92b0811c55c6c03f086e0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga651ea64178b92b0811c55c6c03f086e0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
<tr class="separator:ga651ea64178b92b0811c55c6c03f086e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab62983c1bfe390cd7adc042fb91cbb5a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab62983c1bfe390cd7adc042fb91cbb5a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT</b>&#160;&#160;&#160;30U</td></tr>
<tr class="separator:gab62983c1bfe390cd7adc042fb91cbb5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac786ce45963aa797cb95b91c8b9b62d6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac786ce45963aa797cb95b91c8b9b62d6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:gac786ce45963aa797cb95b91c8b9b62d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f7280cd0f8624b6de99fec9d9a469a5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0f7280cd0f8624b6de99fec9d9a469a5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK</b>&#160;&#160;&#160;0X40000000U</td></tr>
<tr class="separator:ga0f7280cd0f8624b6de99fec9d9a469a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafccf7cc820b6e40f393c30e8476952b4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafccf7cc820b6e40f393c30e8476952b4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_MASK_EN_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:gafccf7cc820b6e40f393c30e8476952b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf073fca2ff52723f8f23808430dcedc0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf073fca2ff52723f8f23808430dcedc0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_MASK_EN_WIDTH</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:gaf073fca2ff52723f8f23808430dcedc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga29d0864253150436c689d353adb40cf5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga29d0864253150436c689d353adb40cf5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_MASK_EN_MASK</b>&#160;&#160;&#160;0X0000FF00U</td></tr>
<tr class="separator:ga29d0864253150436c689d353adb40cf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga138a8001a0f62594564c96e6398ecd5a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga138a8001a0f62594564c96e6398ecd5a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga138a8001a0f62594564c96e6398ecd5a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7f2421588a71d5104922416e8b9469a0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7f2421588a71d5104922416e8b9469a0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:ga7f2421588a71d5104922416e8b9469a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b8d3a39d3a1ede6b87bb11bf3e15a43"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1b8d3a39d3a1ede6b87bb11bf3e15a43"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_POLL_CFG_DATA_VALUE_MASK</b>&#160;&#160;&#160;0X000000FFU</td></tr>
<tr class="separator:ga1b8d3a39d3a1ede6b87bb11bf3e15a43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga311de6f25e5cf64057e9ba429cf86507"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga311de6f25e5cf64057e9ba429cf86507"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_P_TO_OFFSET</b>&#160;&#160;&#160;0X00000058U</td></tr>
<tr class="separator:ga311de6f25e5cf64057e9ba429cf86507"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae85c78b01490ee607527f2147ebf9a4e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae85c78b01490ee607527f2147ebf9a4e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_P_TO_VALUE_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:gae85c78b01490ee607527f2147ebf9a4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca4d95388925cc92cd116fccf9220164"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaca4d95388925cc92cd116fccf9220164"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_P_TO_VALUE_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
<tr class="separator:gaca4d95388925cc92cd116fccf9220164"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga67e9f14a5632e5c8504c7ba185f6b377"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga67e9f14a5632e5c8504c7ba185f6b377"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_P_TO_VALUE_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
<tr class="separator:ga67e9f14a5632e5c8504c7ba185f6b377"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Transfer Status Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for transfer status </p>
</div></td></tr>
<tr class="memitem:ga4951a0b7d9ce35780f74864a196092e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga4951a0b7d9ce35780f74864a196092e4">XQSPIPSU_XFER_STS_OFFSET</a>&#160;&#160;&#160;0X0000005CU</td></tr>
<tr class="memdesc:ga4951a0b7d9ce35780f74864a196092e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_XFER_STS.  <a href="group__qspipsu.html#ga4951a0b7d9ce35780f74864a196092e4">More...</a><br/></td></tr>
<tr class="separator:ga4951a0b7d9ce35780f74864a196092e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fd56f9440b15af05ac96a196b4c4650"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1fd56f9440b15af05ac96a196b4c4650"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga1fd56f9440b15af05ac96a196b4c4650"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8022ff211d2c8ff3c13bff6728dfb26"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac8022ff211d2c8ff3c13bff6728dfb26"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
<tr class="separator:gac8022ff211d2c8ff3c13bff6728dfb26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf924c241bb415ac88853733bc975ed12"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf924c241bb415ac88853733bc975ed12"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_XFER_STS_PEND_BYTES_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
<tr class="separator:gaf924c241bb415ac88853733bc975ed12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU GEN_FIFO Snapshot Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring GENFIFO </p>
</div></td></tr>
<tr class="memitem:gadda8c30c269feb26bc40f588da2c6097"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gadda8c30c269feb26bc40f588da2c6097">XQSPIPSU_GF_SNAPSHOT_OFFSET</a>&#160;&#160;&#160;0X00000060U</td></tr>
<tr class="memdesc:gadda8c30c269feb26bc40f588da2c6097"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_GF_SNAPSHOT.  <a href="group__qspipsu.html#gadda8c30c269feb26bc40f588da2c6097">More...</a><br/></td></tr>
<tr class="separator:gadda8c30c269feb26bc40f588da2c6097"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93a3cc75451b27f6559983b76e18911e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga93a3cc75451b27f6559983b76e18911e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GF_SNAPSHOT_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga93a3cc75451b27f6559983b76e18911e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ca954e0863135e1ba9b64cddc764f60"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6ca954e0863135e1ba9b64cddc764f60"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GF_SNAPSHOT_WIDTH</b>&#160;&#160;&#160;20U</td></tr>
<tr class="separator:ga6ca954e0863135e1ba9b64cddc764f60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdd5572319c31ce9e0a4e2e34622c1d6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafdd5572319c31ce9e0a4e2e34622c1d6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GF_SNAPSHOT_MASK</b>&#160;&#160;&#160;0X000FFFFFU</td></tr>
<tr class="separator:gafdd5572319c31ce9e0a4e2e34622c1d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Receive Data Copy Register information</div></td></tr>
<tr class="memitem:ga419ba63e8028ea7e8aa833523ea3a785"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga419ba63e8028ea7e8aa833523ea3a785">XQSPIPSU_RX_COPY_OFFSET</a>&#160;&#160;&#160;0X00000064U</td></tr>
<tr class="memdesc:ga419ba63e8028ea7e8aa833523ea3a785"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_RX_COPY.  <a href="group__qspipsu.html#ga419ba63e8028ea7e8aa833523ea3a785">More...</a><br/></td></tr>
<tr class="separator:ga419ba63e8028ea7e8aa833523ea3a785"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafda8bb05c3ae9966da0a4ee2912b4d9e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafda8bb05c3ae9966da0a4ee2912b4d9e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_COPY_UPPER_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:gafda8bb05c3ae9966da0a4ee2912b4d9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7e2db1ba9f810863b5b5931c14f5624b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7e2db1ba9f810863b5b5931c14f5624b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_COPY_UPPER_WIDTH</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:ga7e2db1ba9f810863b5b5931c14f5624b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab88c2334a6c2daa47aef99b8a274f18"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaab88c2334a6c2daa47aef99b8a274f18"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_COPY_UPPER_MASK</b>&#160;&#160;&#160;0X0000FF00U</td></tr>
<tr class="separator:gaab88c2334a6c2daa47aef99b8a274f18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga993052dd4aa7866b3dcbf7490149193b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga993052dd4aa7866b3dcbf7490149193b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_COPY_LOWER_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:ga993052dd4aa7866b3dcbf7490149193b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga957493785248c5762016e67eb2ecc8e6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga957493785248c5762016e67eb2ecc8e6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_COPY_LOWER_WIDTH</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:ga957493785248c5762016e67eb2ecc8e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee37c159c17dec939074401a938d66ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaee37c159c17dec939074401a938d66ee"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_RX_COPY_LOWER_MASK</b>&#160;&#160;&#160;0X000000FFU</td></tr>
<tr class="separator:gaee37c159c17dec939074401a938d66ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Module Identification Register information</div></td></tr>
<tr class="memitem:ga9dae139fcca838438b3e14f4306f1f06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga9dae139fcca838438b3e14f4306f1f06">XQSPIPSU_MOD_ID_OFFSET</a>&#160;&#160;&#160;0X000000FCU</td></tr>
<tr class="memdesc:ga9dae139fcca838438b3e14f4306f1f06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_MOD_ID.  <a href="group__qspipsu.html#ga9dae139fcca838438b3e14f4306f1f06">More...</a><br/></td></tr>
<tr class="separator:ga9dae139fcca838438b3e14f4306f1f06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc9f034e70b42b5416121e711a0cbe95"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadc9f034e70b42b5416121e711a0cbe95"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_MOD_ID_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
<tr class="separator:gadc9f034e70b42b5416121e711a0cbe95"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ece64f34919ab3b1e9cb10cf1c01df2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5ece64f34919ab3b1e9cb10cf1c01df2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_MOD_ID_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
<tr class="separator:ga5ece64f34919ab3b1e9cb10cf1c01df2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33cc8bc84990ebd02f0c3ce61d1b6b33"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga33cc8bc84990ebd02f0c3ce61d1b6b33"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_MOD_ID_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU DMA Transfer Register information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains bits for configuring DMA </p>
</div></td></tr>
<tr class="memitem:ga3b9c82ef758ea9e8bfda707130051091"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga3b9c82ef758ea9e8bfda707130051091">XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET</a>&#160;&#160;&#160;0X00000700U</td></tr>
<tr class="memdesc:ga3b9c82ef758ea9e8bfda707130051091"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register: XQSPIPSU_QSPIDMA_DST_ADDR.  <a href="group__qspipsu.html#ga3b9c82ef758ea9e8bfda707130051091">More...</a><br/></td></tr>
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<tr class="memitem:gab993adfc8d3e5fd256f46c9543ce7299"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab993adfc8d3e5fd256f46c9543ce7299"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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<tr class="memitem:gac6ab554d9ab60514d9e9b22260d9f6e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac6ab554d9ab60514d9e9b22260d9f6e5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH</b>&#160;&#160;&#160;30U</td></tr>
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<tr class="memitem:gacb00be2007021a12b97d6282fb2bca5a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacb00be2007021a12b97d6282fb2bca5a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_MASK</b>&#160;&#160;&#160;0XFFFFFFFCU</td></tr>
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<tr class="memitem:gab2dea188a0404d6e555c4ff2839eb86a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab2dea188a0404d6e555c4ff2839eb86a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET</b>&#160;&#160;&#160;0X00000704U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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<tr class="memitem:ga5c70ae2a63d008b335e51d9e3f71c4c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5c70ae2a63d008b335e51d9e3f71c4c9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH</b>&#160;&#160;&#160;27U</td></tr>
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<tr class="memitem:gac3a77c17cdc599e640dadd63d60b21ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3a77c17cdc599e640dadd63d60b21ab"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_SIZE_MASK</b>&#160;&#160;&#160;0X1FFFFFFCU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_OFFSET</b>&#160;&#160;&#160;0X00000708U</td></tr>
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<tr class="memitem:ga92c00900dc411f8f09b99913f96dd37e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga92c00900dc411f8f09b99913f96dd37e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT</b>&#160;&#160;&#160;13U</td></tr>
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<tr class="memitem:ga964e0fee9789a290fcace60880702ad0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga964e0fee9789a290fcace60880702ad0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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<tr class="memitem:ga93dc8fe59720d81079c993682e5bf310"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga93dc8fe59720d81079c993682e5bf310"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK</b>&#160;&#160;&#160;0X0000E000U</td></tr>
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<tr class="memitem:gaa5a88d98f9a05c1b3636a81a93f6c2e3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa5a88d98f9a05c1b3636a81a93f6c2e3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
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<tr class="memitem:ga751c35c56034073e8e1ca0dd8d9f9bfb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga751c35c56034073e8e1ca0dd8d9f9bfb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH</b>&#160;&#160;&#160;8U</td></tr>
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<tr class="memitem:gadc2dbd0dfe87b5adf440e9001c4658b3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadc2dbd0dfe87b5adf440e9001c4658b3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK</b>&#160;&#160;&#160;0X00001FE0U</td></tr>
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<tr class="memitem:ga7f20515e77a83b8acb0010b7d788fe75"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7f20515e77a83b8acb0010b7d788fe75"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gad51955f7901e0a5b8b62fb0f614be027"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad51955f7901e0a5b8b62fb0f614be027"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH</b>&#160;&#160;&#160;4U</td></tr>
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<tr class="memitem:gafd6f55d877c432a60099d8b4d8734e39"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafd6f55d877c432a60099d8b4d8734e39"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK</b>&#160;&#160;&#160;0X0000001EU</td></tr>
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<tr class="memitem:gaecec61c2aace2c0586f5c9b0491c65f3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaecec61c2aace2c0586f5c9b0491c65f3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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<tr class="memitem:ga19664047f57d0b6d5897c97927367978"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga19664047f57d0b6d5897c97927367978"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:ga28a7180c7ddc44364157dd75666718d4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga28a7180c7ddc44364157dd75666718d4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
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<tr class="memitem:gad5b1b0d090cd0e7ba952d165349358f2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad5b1b0d090cd0e7ba952d165349358f2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_STS_WTC</b>&#160;&#160;&#160;0xE000U</td></tr>
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<tr class="memitem:ga1c49b7d688c394b3bb37d4293fa34df5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c49b7d688c394b3bb37d4293fa34df5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET</b>&#160;&#160;&#160;0X0000070CU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT</b>&#160;&#160;&#160;25U</td></tr>
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<tr class="memitem:ga83c7d22d0a1cad6eb84224213cc6124d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga83c7d22d0a1cad6eb84224213cc6124d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH</b>&#160;&#160;&#160;7U</td></tr>
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<tr class="memitem:gaab8f3ed04924c50ac623beda99450b20"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaab8f3ed04924c50ac623beda99450b20"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK</b>&#160;&#160;&#160;0XFE000000U</td></tr>
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<tr class="memitem:ga863cb44339ed10347558e304166e7b1e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga863cb44339ed10347558e304166e7b1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT</b>&#160;&#160;&#160;24U</td></tr>
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<tr class="memitem:gaed4d839a0b110c93ba907ed2d39de3b6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaed4d839a0b110c93ba907ed2d39de3b6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gafaa404a9e4a5137615a1bb0205d54798"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafaa404a9e4a5137615a1bb0205d54798"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK</b>&#160;&#160;&#160;0X01000000U</td></tr>
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<tr class="memitem:gabb6c6d1f62756a0c22fc8caae2cf5187"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabb6c6d1f62756a0c22fc8caae2cf5187"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT</b>&#160;&#160;&#160;23U</td></tr>
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<tr class="memitem:ga179fa006eced0e96ae2ec3f6e54350f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga179fa006eced0e96ae2ec3f6e54350f0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gabd1f950015647ad4badc0554b06f4d33"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd1f950015647ad4badc0554b06f4d33"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK</b>&#160;&#160;&#160;0X00800000U</td></tr>
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<tr class="memitem:ga809ad867b6ee031e5a54445d077edc14"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga809ad867b6ee031e5a54445d077edc14"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT</b>&#160;&#160;&#160;22U</td></tr>
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<tr class="memitem:ga561e23d469b3e62a22b70de380173d66"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga561e23d469b3e62a22b70de380173d66"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
<tr class="separator:ga561e23d469b3e62a22b70de380173d66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga48d0c63798b35da7ca3c4a4e5eb93c1e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga48d0c63798b35da7ca3c4a4e5eb93c1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK</b>&#160;&#160;&#160;0X00400000U</td></tr>
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<tr class="memitem:ga4c73d6f9e015b79b55d3fc23f87ae548"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4c73d6f9e015b79b55d3fc23f87ae548"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT</b>&#160;&#160;&#160;10U</td></tr>
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<tr class="memitem:ga2258b69501bd844fd3e03a89dd574bfd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2258b69501bd844fd3e03a89dd574bfd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH</b>&#160;&#160;&#160;12U</td></tr>
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<tr class="memitem:gab33bc2f0ad94595f39219b3d95646e1e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab33bc2f0ad94595f39219b3d95646e1e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK</b>&#160;&#160;&#160;0X003FFC00U</td></tr>
<tr class="separator:gab33bc2f0ad94595f39219b3d95646e1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf63e637aca6336a6fbe5a026c3702061"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf63e637aca6336a6fbe5a026c3702061"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
<tr class="separator:gaf63e637aca6336a6fbe5a026c3702061"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d2c335236305825a111a0e305395cba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7d2c335236305825a111a0e305395cba"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:ga7d2c335236305825a111a0e305395cba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7191f7e5faad4dffadbdc79efdf8d47"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa7191f7e5faad4dffadbdc79efdf8d47"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK</b>&#160;&#160;&#160;0X000003FCU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK</b>&#160;&#160;&#160;0X00000001U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL</b>&#160;&#160;&#160;0x403FFA00U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET</b>&#160;&#160;&#160;0X00000714U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT</b>&#160;&#160;&#160;6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK</b>&#160;&#160;&#160;0X00000040U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK</b>&#160;&#160;&#160;0X000000FCU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK</b>&#160;&#160;&#160;0X000000FEU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET</b>&#160;&#160;&#160;0X00000718U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT</b>&#160;&#160;&#160;6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK</b>&#160;&#160;&#160;0X00000040U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET</b>&#160;&#160;&#160;0X0000071CU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT</b>&#160;&#160;&#160;6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK</b>&#160;&#160;&#160;0X00000040U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_OFFSET</b>&#160;&#160;&#160;0X00000720U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT</b>&#160;&#160;&#160;7U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK</b>&#160;&#160;&#160;0X00000080U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT</b>&#160;&#160;&#160;6U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK</b>&#160;&#160;&#160;0X00000040U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT</b>&#160;&#160;&#160;5U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK</b>&#160;&#160;&#160;0X00000020U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
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<tr class="memitem:gaa736fba149e752cdde498124580e55d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa736fba149e752cdde498124580e55d1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK</b>&#160;&#160;&#160;0X00000010U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT</b>&#160;&#160;&#160;3U</td></tr>
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<tr class="memitem:gaebb5419ad726384a6848b0b55f0f4dd5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaebb5419ad726384a6848b0b55f0f4dd5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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<tr class="memitem:gaa7e0f93ceb34aaf37b4857a97ae672aa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa7e0f93ceb34aaf37b4857a97ae672aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK</b>&#160;&#160;&#160;0X00000008U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT</b>&#160;&#160;&#160;2U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK</b>&#160;&#160;&#160;0X00000004U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK</b>&#160;&#160;&#160;0X00000002U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET</b>&#160;&#160;&#160;0X00000724U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT</b>&#160;&#160;&#160;27U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK</b>&#160;&#160;&#160;0X08000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT</b>&#160;&#160;&#160;24U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK</b>&#160;&#160;&#160;0X07000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT</b>&#160;&#160;&#160;22U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK</b>&#160;&#160;&#160;0X00400000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT</b>&#160;&#160;&#160;19U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK</b>&#160;&#160;&#160;0X00380000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT</b>&#160;&#160;&#160;16U</td></tr>
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<tr class="memitem:ga0a1af0bab0712b0e003d5349988a4c7d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0a1af0bab0712b0e003d5349988a4c7d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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<tr class="memitem:ga99d0e899aaaa748f7d862dc1b81d6320"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga99d0e899aaaa748f7d862dc1b81d6320"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK</b>&#160;&#160;&#160;0X00070000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT</b>&#160;&#160;&#160;4U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH</b>&#160;&#160;&#160;12U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK</b>&#160;&#160;&#160;0X0000FFF0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH</b>&#160;&#160;&#160;4U</td></tr>
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<tr class="memitem:gacd88b1d57388f468a09208ed57e002aa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd88b1d57388f468a09208ed57e002aa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK</b>&#160;&#160;&#160;0X0000000FU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET</b>&#160;&#160;&#160;0X00000728U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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<tr class="memitem:ga26f769aa9e3c62220857e6db8c1e2212"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga26f769aa9e3c62220857e6db8c1e2212"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH</b>&#160;&#160;&#160;12U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK</b>&#160;&#160;&#160;0X00000FFFU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET</b>&#160;&#160;&#160;0X00000EFCU</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT</b>&#160;&#160;&#160;0U</td></tr>
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<tr class="memitem:ga07a8c2c8600afaaabed4bf1bd9899205"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07a8c2c8600afaaabed4bf1bd9899205"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH</b>&#160;&#160;&#160;32U</td></tr>
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<tr class="memitem:ga706a6f83a128361fb2cf5383ede70157"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga706a6f83a128361fb2cf5383ede70157"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK</b>&#160;&#160;&#160;0XFFFFFFFFU</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU Generic FIFO masks information</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Generic FIFO masks information </p>
</div></td></tr>
<tr class="memitem:gaa8a6c468b32dd07920d5a47ec6294d79"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gaa8a6c468b32dd07920d5a47ec6294d79">XQSPIPSU_GENFIFO_IMM_DATA_MASK</a>&#160;&#160;&#160;0xFFU</td></tr>
<tr class="memdesc:gaa8a6c468b32dd07920d5a47ec6294d79"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generic FIFO masks.  <a href="group__qspipsu.html#gaa8a6c468b32dd07920d5a47ec6294d79">More...</a><br/></td></tr>
<tr class="separator:gaa8a6c468b32dd07920d5a47ec6294d79"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_DATA_XFER</b>&#160;&#160;&#160;0x100U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_EXP</b>&#160;&#160;&#160;0x200U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_MODE_SPI</b>&#160;&#160;&#160;0x400U</td></tr>
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<tr class="memitem:ga8261c65f81af4f5d8f8d8419bd9ce16a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8261c65f81af4f5d8f8d8419bd9ce16a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_MODE_DUALSPI</b>&#160;&#160;&#160;0x800U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_MODE_QUADSPI</b>&#160;&#160;&#160;0xC00U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_MODE_MASK</b>&#160;&#160;&#160;0xC00U	/* And with ~MASK first */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_CS_LOWER</b>&#160;&#160;&#160;0x1000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_CS_UPPER</b>&#160;&#160;&#160;0x2000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_BUS_LOWER</b>&#160;&#160;&#160;0x4000U</td></tr>
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<tr class="memitem:ga90863432a0e1c93a8d3c4840a5046312"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga90863432a0e1c93a8d3c4840a5046312"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_BUS_UPPER</b>&#160;&#160;&#160;0x8000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_BUS_BOTH</b>&#160;&#160;&#160;0xC000U	/* inverse is no bus */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_BUS_MASK</b>&#160;&#160;&#160;0xC000U	/* And with ~MASK first */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_TX</b>&#160;&#160;&#160;0x10000U	/* inverse is zero pump */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_RX</b>&#160;&#160;&#160;0x20000U	/* inverse is RX discard */</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_STRIPE</b>&#160;&#160;&#160;0x40000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_GENFIFO_POLL</b>&#160;&#160;&#160;0x80000U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">XQSPIPSU RX Data Delay Register information</div></td></tr>
<tr class="memitem:gab365948c6ecd1f11c876a6b374e17194"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#gab365948c6ecd1f11c876a6b374e17194">XQSPIPSU_DATA_DLY_ADJ_OFFSET</a>&#160;&#160;&#160;0X000000F8U</td></tr>
<tr class="memdesc:gab365948c6ecd1f11c876a6b374e17194"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI Data delay register.  <a href="group__qspipsu.html#gab365948c6ecd1f11c876a6b374e17194">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT</b>&#160;&#160;&#160;31U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH</b>&#160;&#160;&#160;1U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK</b>&#160;&#160;&#160;0X80000000U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT</b>&#160;&#160;&#160;28U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH</b>&#160;&#160;&#160;3U</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XQSPIPSU_DATA_DLY_ADJ_DLY_MASK</b>&#160;&#160;&#160;0X70000000U</td></tr>
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<tr><td colspan="2"><div class="groupHeader">TAPDLY Bypass register information</div></td></tr>
<tr class="memitem:ga0bbc5a63a23f12de8b6feb217e0f317b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__qspipsu.html#ga0bbc5a63a23f12de8b6feb217e0f317b">IOU_TAPDLY_BYPASS_OFFSET</a>&#160;&#160;&#160;0X00000390U</td></tr>
<tr class="memdesc:ga0bbc5a63a23f12de8b6feb217e0f317b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tapdelay Bypass register.  <a href="group__qspipsu.html#ga0bbc5a63a23f12de8b6feb217e0f317b">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT</b>&#160;&#160;&#160;0X02U</td></tr>
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<tr class="memitem:gacc733c5b377c27d5aee44ce762dc94b2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacc733c5b377c27d5aee44ce762dc94b2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH</b>&#160;&#160;&#160;0X01U</td></tr>
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<tr class="memitem:ga18d189b90381866973330f5cdd110b26"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga18d189b90381866973330f5cdd110b26"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>IOU_TAPDLY_BYPASS_LQSPI_RX_MASK</b>&#160;&#160;&#160;0x00000004U</td></tr>
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<tr class="memitem:ga27c3393df4ae5b7819435ca0f970007f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga27c3393df4ae5b7819435ca0f970007f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>IOU_TAPDLY_RESET_STATE</b>&#160;&#160;&#160;0x7U</td></tr>
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